8 External Interrupts
1. Set IRQ0 (PB4), which is triggered by rising edge.
clr P_IRQ_Opt1,CB_IRQOpt1_IRQM0
clr P_IRQ_Opt1,CB_IRQOpt1_IRQM0
; IRQ0 edge trigger
set P_IRQ_Opt1,CB_IRQOpt1_IRQ0ES
set P_IRQ_Opt1,CB_IRQOpt1_IRQ0ES
; IRQ0 rising trigger
set P_INT_Flag0,CB_INT_IRQ0IF
; clear INT request flag
set P_INT_Ctrl0,CB_INT_IRQ0IE
; enable IRQ0 INT (INT1).
cli ; enable INT
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2. Set IRQ0 (PB4), which is triggered by falling edge.
clr P_IRQ_Opt1,CB_IRQOpt1_IRQM0
clr P_IRQ_Opt1,CB_IRQOpt1_IRQM0
; IRQ0 edge trigger
clr P_IRQ_Opt1,CB_IRQOpt1_IRQ0ES
clr P_IRQ_Opt1,CB_IRQOpt1_IRQ0ES
; IRQ0 falling trigger
set P_INT_Flag0,CB_INT_IRQ0IF
; clear INT request flag
set P_INT_Ctrl0,CB_INT_IRQ0IE
; enable IRQ1 INT (INT1).
cli ; enable INT |
3. Set IRQ0 (PB4), which is triggered by high level.
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set P_IRQ_Opt1,CB_IRQOpt1_IRQM0
set P_IRQ_Opt1,CB_IRQOpt1_IRQM0
; IRQ0 level trigger
set P_IRQ_Opt1,CB_IRQOpt1_IRQ0ES
set P_IRQ_Opt1,CB_IRQOpt1_IRQ0ES
; IRQ0 rising level trigger
set P_INT_Flag0,CB_INT_IRQ0IF
; clear INT request flag
set P_INT_Ctrl0,CB_INT_IRQ0IE
; enable IRQ1 INT (INT1).
cli ; enable INT
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4. Set IRQ0 (PB4), which is triggered by low level.
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set P_IRQ_Opt1,CB_IRQOpt1_IRQM0
set P_IRQ_Opt1,CB_IRQOpt1_IRQM0
; IRQ0 level trigger
clr P_IRQ_Opt1,CB_IRQOpt1_IRQ0ES
clr P_IRQ_Opt1,CB_IRQOpt1_IRQ0ES
; IRQ0 falling level trigger
set P_INT_Flag0,CB_INT_IRQ0IF
; clear INT request flag
set P_INT_Ctrl0,CB_INT_IRQ0IE
; enable IRQ1 INT (INT1).
cli ; enable INT
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5. Set IRQ1 (PB5), which is triggered by rising edge.
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clr P_IRQ_Opt1,CB_IRQOpt1_IRQM1
clr P_IRQ_Opt1,CB_IRQOpt1_IRQM1
; IRQ1 edge trigger
set P_IRQ_Opt1,CB_IRQOpt1_IRQ1ES
set P_IRQ_Opt1,CB_IRQOpt1_IRQ1ES
; IRQ1 rising trigger
set P_INT_Flag0,CB_INT_IRQ1IF
; clear INT request flag
set P_INT_Ctrl0,CB_INT_IRQ1IE
; enable IRQ1 INT (INT1).
cli ; enable INT
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6. Set IRQ1 (PB5), which is triggered by falling edge.
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clr P_IRQ_Opt1,CB_IRQOpt1_IRQM1
clr P_IRQ_Opt1,CB_IRQOpt1_IRQM1
; IRQ1 edge trigger
clr P_IRQ_Opt1,CB_IRQOpt1_IRQ1ES
clr P_IRQ_Opt1,CB_IRQOpt1_IRQ1ES
; IRQ1 falling trigger
set P_INT_Flag0,CB_INT_IRQ1IF
; clear INT request flag
set P_INT_Ctrl0,CB_INT_IRQ1IE
; enable IRQ1 INT (INT1).
cli ; enable INT
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7. Set IRQ1 (PB5), which is triggered by high level.
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set P_IRQ_Opt1,CB_IRQOpt1_IRQM1
set P_IRQ_Opt1,CB_IRQOpt1_IRQM1
; IRQ1 level trigger
set P_IRQ_Opt1,CB_IRQOpt1_IRQ1ES
set P_IRQ_Opt1,CB_IRQOpt1_IRQ1ES
; IRQ1 high level trigger
set P_INT_Flag0,CB_INT_IRQ1IF
; clear INT request flag
set P_INT_Ctrl0,CB_INT_IRQ1IE
; enable IRQ1 INT (INT1).
cli ; enable INT
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8. Set IRQ1 (PB5), which is triggered by low level.
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set P_IRQ_Opt1,CB_IRQOpt1_IRQM1
set P_IRQ_Opt1,CB_IRQOpt1_IRQM1
; IRQ1 level trigger
clr P_IRQ_Opt1,CB_IRQOpt1_IRQ1ES
clr P_IRQ_Opt1,CB_IRQOpt1_IRQ1ES
; IRQ1 low level trigger
set P_INT_Flag0,CB_INT_IRQ1IF
; clear INT request flag
set P_INT_Ctrl0,CB_INT_IRQ1IE
; enable IRQ1 INT (INT1).
cli ; enable INT
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9. Set IRQ2 (PD0), which is triggered by rising edge.
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clr P_IRQ_Opt1,CB_IRQOpt1_IRQM2
clr P_IRQ_Opt1,CB_IRQOpt1_IRQM2
; IRQ2 edge trigger
set P_IRQ_Opt1,CB_IRQOpt1_IRQ2ES
set P_IRQ_Opt1,CB_IRQOpt1_IRQ2ES
; IRQ2 rising trigger
set P_INT_Flag0,CB_INT_IRQ2IF
; clear INT request flag
set P_INT_Ctrl0,CB_INT_IRQ2IE
; enable IRQ2 INT (INT1).
cli ; enable INT
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10. Set IRQ2 (PD0), which is triggered by falling edge.
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clr P_IRQ_Opt1,CB_IRQOpt1_IRQM2
clr P_IRQ_Opt1,CB_IRQOpt1_IRQM2
; IRQ2 edge trigger
clr P_IRQ_Opt1,CB_IRQOpt1_IRQ2ES
clr P_IRQ_Opt1,CB_IRQOpt1_IRQ2ES
; IRQ2 falling trigger
set P_INT_Flag0,CB_INT_IRQ2IF
; clear INT request flag
set P_INT_Ctrl0,CB_INT_IRQ2IE
; enable IRQ2 INT (INT1).
cli ; enable INT
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11. Set IRQ2 (PD0), which is triggered by high level.
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set P_IRQ_Opt1,CB_IRQOpt1_IRQM2
set P_IRQ_Opt1,CB_IRQOpt1_IRQM2
; IRQ2 level trigger
set P_IRQ_Opt1,CB_IRQOpt1_IRQ2ES
set P_IRQ_Opt1,CB_IRQOpt1_IRQ2ES
; IRQ2 high level trigger
set P_INT_Flag0,CB_INT_IRQ2IF
; clear INT request flag
set P_INT_Ctrl0,CB_INT_IRQ2IE
; enable IRQ2 INT (INT1).
cli ; enable INT
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12. Set IRQ2 (PD0), which is triggered by low level.
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set P_IRQ_Opt1,CB_IRQOpt1_IRQM2
set P_IRQ_Opt1,CB_IRQOpt1_IRQM2
; IRQ2 level trigger
clr P_IRQ_Opt1,CB_IRQOpt1_IRQ2ES
clr P_IRQ_Opt1,CB_IRQOpt1_IRQ2ES
; IRQ2 low level trigger
set P_INT_Flag0,CB_INT_IRQ2IF
; clear INT request flag
set P_INT_Ctrl0,CB_INT_IRQ2IE
; enable IRQ2 INT (INT1).
cli ; enable INT
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13. Set IRQ3 (PD1), which is triggered by rising edge.
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clr P_IRQ_Opt1,CB_IRQOpt1_IRQM3
clr P_IRQ_Opt1,CB_IRQOpt1_IRQM3
; IRQ3 edge trigger
set P_IRQ_Opt1,CB_IRQOpt1_IRQ3ES
set P_IRQ_Opt1,CB_IRQOpt1_IRQ3ES
; IRQ3 rising trigger
set P_INT_Flag0,CB_INT_IRQ3IF
; clear INT request flag
set P_INT_Ctrl0,CB_INT_IRQ3IE
; enable IRQ3 INT (INT1).
cli ; enable INT
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14. Set IRQ3 (PD1), which is triggered by falling edge.
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clr P_IRQ_Opt1,CB_IRQOpt1_IRQM3
clr P_IRQ_Opt1,CB_IRQOpt1_IRQM3
; IRQ3 edge trigger
clr P_IRQ_Opt1,CB_IRQOpt1_IRQ3ES
clr P_IRQ_Opt1,CB_IRQOpt1_IRQ3ES
; IRQ3 falling trigger
set P_INT_Flag0,CB_INT_IRQ3IF
; clear INT request flag
set P_INT_Ctrl0,CB_INT_IRQ3IE
; enable IRQ3 INT (INT1).
cli ; enable INT
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15. Set IRQ3 (PD1), which is triggered by high level.
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set P_IRQ_Opt1,CB_IRQOpt1_IRQM3
set P_IRQ_Opt1,CB_IRQOpt1_IRQM3
; IRQ3 level trigger
set P_IRQ_Opt1,CB_IRQOpt1_IRQ3ES
set P_IRQ_Opt1,CB_IRQOpt1_IRQ3ES
; IRQ3 high level trigger
set P_INT_Flag0,CB_INT_IRQ3IF
; clear INT request flag
set P_INT_Ctrl0,CB_INT_IRQ3IE
; enable IRQ3 INT (INT1).
cli ; enable INT
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16. Set IRQ3 (PD1), which is triggered by low level.
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set P_IRQ_Opt1,CB_IRQOpt1_IRQM3
set P_IRQ_Opt1,CB_IRQOpt1_IRQM3
; IRQ3 level trigger
clr P_IRQ_Opt1,CB_IRQOpt1_IRQ3ES
clr P_IRQ_Opt1,CB_IRQOpt1_IRQ3ES
; IRQ3 low level trigger
set P_INT_Flag0,CB_INT_IRQ3IF
; clear INT request flag
set P_INT_Ctrl0,CB_INT_IRQ3IE
; enable IRQ3 INT (INT1).
cli ; enable INT
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