Hardware Development Tool FAQ

Q: Can we use a target board to provide the system clock when running with an emulator? A: No, default crystal oscillator is built in the emulator. In the process of emulation the crystal oscillator in the target board doesn"t work. Q: What's the frequency of the crystal oscillation in the emulator? How to change the frequency of it? A: The frequency of the crystal oscillator in the emulator is 16M Hz. The crystal oscillator is fixed inside the emulator, and the frequency is not changeable in any other places. The only way to change the frequency is to open the iron hull of the emulator and change the 16M Hz crystal device into another with a different frequency. Q：Can ceramic crystal oscillator be used? A: Yes, but the iron hull of the emulator must be opened and the 16M Hz crystal oscillator should be replaced with ceramic crystal oscillator. Q: Can RC oscillator be used? A: Yes, but the iron hull of the emulator must be opened and the 16M Hz crystal oscillator should be replaced with RC. Q: Can a target board be used to supply power for the emulator? A: Yes, but only +5V can be used as the power supply for the emulator, soon we"ll consider 3.3V. Q: The crystal oscillator that is shown in the schematic is 16M, but in the reference book the max. operating frequency of the system is 8M Hz, which one is exact? A: The frequency of the external crystal oscillator is 16M Hz. After divided by PLL built in IC, it is half (8M Hz) for the system. Q: How are IOs of the external socket assigned? A: See the following figure:

Software Development Tool FAQ Q：After a project is created in FortisIDE, various file types are found in the WorkSpace window. What are they? A: A project includes all the information for creating a specific program. A newly created project should include 8 types of files: *.spj, *.rc, *.set, *.env*, *.asm, prog.lik, *.cmd, *.inc. After the project is built, FortisIDE will automatically add these 8 files into it. 1. *.spj, *.rc, *.set, *.env (with the same name as the project): System Files. .spj can represent the type of a project file. Users can open a project through clicking a *.spj file. 2. *.asm: Assemble Language Program Files 3. prog.lik: It can direct the linker to link object files. Open this file and directly modify the contents in the file. 4. *.cmd (with the same name as the project): It can inform the ICE / emulation board how to download binary files (.tsk /.bin), namely to decide file mapping on ICE and emulation board. 5. *.inc: Head File. It defines every I/O port and hardware register and it must be contained in sound codes. Q: What is library function? How can it be loaded to the project? A: The Library Function is a .lib file, that is, a function set, where the function name, object code, and reset bit information for linking of every function are stored. If a certain function in the library is called by user program, it will be loaded into the project. In the process of linking, the linker will directly embed corresponding function code into the executable file for user program. The way to load the function library is as follows: Open Project→Setting→Link, and, the Setting dialog is popped up, then load library file to the project. See the following figure. Q: What's the basic step to develop with FortisIDE? A: FortisIDE can normally work with an in-circuit emulation board. Usually, the developing procedure is as follows: Create a Project→Set the Project→Manage the Project→Compile the Project→Run the Project→Debug the Project. Q: Does FortisIDE have the program run tracking function? Where? How to look it over? A: Yes, it does. User can enable the function after doing the following configuration: 1. Enable PC Track Enable option in Device page after the selections of Project→Setting→Device; 2. Compile at full speed; 3. Run the program freely and click the Break button; 4. Click "T" button in the toolbar. Q: After creating a project in FortisIDE, Main.asm file will automatically generate. What's the function of this file? How to use it? A: Main.asm, an assemble language program file generated automatically in the system, perfectly contains all the requisite statements for a program. Thereinto, "PAGE0" is used to define zero page variable; "DATA" to define non-zero page variable; "CODE" to write your program; and "VECTOR" to define interrupt entry address. Users only need to write program following V_Reset:. ;**************************************** ;* * ;*Power on Reset Process - Main Program * ;* * ;**************************************** .PUBLIC V_Reset ; V_Reset: Q: What's the meaning of PB2 Reservation in the reference book? A: It means the operation of this bit is meaningless. Q: Does FortisIDE-V1.6.5.1 support C language programming? A: So far FortisIDE-V1.6.5.1 doesn"t support C language programming. Q: Why is the 10ms timer not accurate and why does the timer not been changed when I change the setting of the high byte of preload register . The program code is as the following: lda　　#01000000b sta　　P_TMR0_1_Ctrl0 lda　　#00110000b sta　　P_TMR0_1_Ctrl1 lda　　#16 sta　　P_TMR1_Preload lda　　#216 sta　　P_TMR1_PreloadHi lda　　#FFh sta　　P_INT_Flag1 set　　P_INT_Ctrl1,1 cli ;set time1 is 16 bit counter ; Set Timer1 clock source is Fsys/8 ;\ ;+ set 10ms ;+ Fsys(8MHz)/8/(40x250)=100Hz ;/ ; clear INT request flag of time1 ; set time1 overflow interupt ; enable INT A: As for 16-bit Timer we must load the high byte P_TMR1_PreloadHi first, then load the low byte P_TMR1_Preload . ?If the load sequence is not so, the setting to timer will be invalid. Q: What contents will be reset if "Reset" button of "Statistic Window" in Q-Writer is pressed? A: Here the system will pop up an information box "All contents will be cleared, continue or not?" to ask users whether to clear all the contents except Target. Q: What will happen if we open the project and start to write codes without selecting any model of MCU when we startup Q-Writer for the first time? A: The system will display warning information and automatically pop up "Select Device" window for user to select a model of MCU. Q: If the MCU are blank, what will happen if we secure the MCU memory through the Q-Writer? A: The system will automatically pop-up a dialog box with a warning "Your IC is blank, Securing prohibited!". That is, to secure a blank MCU is not permitted. Q: Q-Writer will display warning information "This sequence number may have been used!" Why? A: In "Auto Increment" mode the serial number will automatically increase or decrease. But when the number overflows by the increment or decrement, a repeated serial number may be appear. If users continue writing, the repeated serial number may be written into more than one chip. Q: How to write chips through Q-Writer? A: The basic process to write with Q-Writer is as follows: Q: How to fix the chip into the writing socket of the in-circuit emulator & programmer before writing? A: The notch of the chip should align with that of writing socket, namely connecting pin 1 of the chip to the writing socket of the in-circuit emulator & programmer. See the following figure: Q: After the writing MCU is secured, whether all the information can"t be read out or not? A: After being secured only system option register, the important user information and the last 16 bytes (0xFFF0~0xFFFF) in the memory. Other contents in it are all read as 0x00.

Package

Q： Is the pin assignment of PDIP accordance with that of SOP for the same type of chip with same pin number? A: Yes.

Operating Mode

Q: How many power supply management modes does SPMC65 family MCU have? And can they be applied to the low power consumption modes? A: SPMC65 family MCU offers three power management modes: NORMAL, STOP and HALT, and thereinto, STOP and HALT are power saving modes. In STOP mode, oscillator, CPU and all peripherals are all disabled; in HALT mode, only CPU is disabled and the peripherals remains active. Thus the power consumption in the HALT mode is greater than that in the STOP mode. Q: In HALT and STOP modes, does Watchdog Timer (WDT) run? A: The clock source of SPMC65 MCU WDT is supplied by the on-chip RC oscillator. In the HALT mode, all the peripherals keep the original running state and run normally, except that CPU stops for power saving; at this time the watchdog runs normally; in the STOP mode, on-chip RC oscillator stops working, CPU and all peripherals also stop. At this time whether the watchdog is enabled lies on the watchdog setting before entering STOP mode, if the watchdog is set to be enabled in the STOP mode, it will run normally and wake up CPU from the STOP mode with watchdog interrupt function; if the watchdog is set to be disabled in the STOP mode, it will stop running. Q: How long does it take from Power-on Reset to Analog-to-Digital Converter (ADC) is ready for running? And how long does it take from that quitting from the STOP mode and entering the normal mode to that ADC is ready for running? A: After Power-On Reset, the ADC setup time is equal to that for settle top reference voltage, which depends on the capacitance of the capacitor connected in VREF pin. The greater the capacitance is, the lower the noise of VREF and ADC conversion result is. If the capacitance is 4.7uF, the setup time is probably 2ms; if there is no by-pass capacitor (not recommendable), the time for settlement is probably 10us. Note: Before AD conversion, tracking time should be 1.5us, which determines the switching speed of ADC multiplexer switch (MUX). After MCU quits from STOP mode and enters the normal operation mode, period from ADC becoming settled to start conversion is equal to that in Power-On Reset. Q: How to set I/O state to get the minimum power consumption in power saving mode? A: In order to save power, those peripherals (ADC module, watchdog) that will not be used temporarily should be disabled before entering the STOP mode. First, set the ports to be input and make sure there is no current flow in the ports and peripheral circuit. As input ports, they have extremely high impendence for the external world. As a result, current will not be generated. The normal input voltage should be VSS or VDD, otherwise, tiny current may be generated (1mA @ 2V.). Therefore, considering peripheral circuit, if the ports are unfit to be set as input, it can be set to be output with a certain level that determined by the external circuit. For instance, if the pin is connected with a pull-up resistor, it can be configured to output high level signal; if pull-down, it can be set to output low level signal. The following figure is to show the schematic diagram for ports when they"re used neither as input nor as output: Q: Why two or more NOP instructions should follow the instructions that for entering HALT or STOP modes? Without these NOP instructions, will the system execute the instructions following the instructions that for entering the HALT or STOP modes? A: Normally, after being waken up from the power saving mode, no user program is run rightly to prevent it from error running resulted by the unstable system clock. Therefore, two or more NOP instructions, that do no operation, should follow the instructions that for entering HALT or STOP modes. In this way, even though NOP is executed before the system clock becomes settlement, the system will not be influenced. It provides more reliability for the system operation. Memory Organization Q: How many bytes does the stack space of SPMC65 family MCU take up? How can a stack generate? A: SPMC65 family MCU takes up 32 bytes at locations $01E0 ~ $01FF, and the direction of the pointer movement is from high address to low, i.e., the initial state stack pointer (SP) points to $01FF; after a data is pushed onto the stack, SP will automatically subtract 1; before a data is popped from the stack, SP will first automatically add 1. Once the pointer is out of $01E0, CPU will execute the Illegal Address Reset (IAR). Q: Stack pointer is an 8-bit register, but after initialization the stack pointer points to $01FFh, why? A: CPU will automatically extend a 9th bit for the stack pointer register and the related bit value in the register always displays 1. Therefore, in the CPU, SP is formed after the stack pointer register has extended the 9th bit. See the following figure: Q: How to use chip configuration option register? A: In SPMC65 family MCU, the device configuration registers takes up 4-byte space namely $7FE0~$7FE3, thereinto, 3 registers are valid and read-only. Through these registers, user can set LVR, WDR, select NMI source, select clock source, and so on. But user can not write data to them; user can firstly config them in Fortis IDE, and then run an in-circuit Emulator & Programmer or a writer joining a computer to writer these information into a chip. Q: Since the pin assigment of SPMC65P2408A 28PIN package is the same as that of SPMC65P2404A; besides, except the memory (ROM and RAM) and partial hardware resources, other resources are the same. Can the program be ported freely if the program space is sufficient? A: Yes, the program can be ported provided that the target device has enough RAM and ROM space. Moreover, it must be ensured that those resources that exist in SPMC65P2408A but not in SPMC65P2404A haven"t been taken in this porting code. Q: Where is the interrupt entrance for every interrupt source on SPMC65 family MCU? A: On SPMC65 family MCU, the vector space is defined at locations $FFFA~$FFFF on the program memory. See the following figure: The reset vectors are stored at locations $FFFC and $FFFD, serving as the program entrance locations after CPU resets. Every NMI vector is stored at locations $FFFA~$FFFB and IRQ (including all interrupts except NMI) vectors are stored at locations $FFFE~$FFFF. The vector address should be defined correctly in the user program. CPU jumps to corresponding interrupt service subroutine through interrupt vector. Q: What's the difference between .PAGE0 and .DATA when defining variable in data memory? A: .PAGE0 is used to define a variable in page0; and .DATA for the non page0 ones. In SPMC65x devices, PAGE0 ranges $0000~$00FF which includes hardware control registers memory and part of user-defined RAM. Other RAM space is provided for DATA segment. The access to page0 is faster than to DATA segment; bit operation instruction can only read and write data in page0. Q: Is there any other requirements for doing double write operations to every bit at locations $30~$36? A: For every double write register, double clearing counter is enabled. After the first write operation, it generates an internal tag; if the register is written with an equal data again, the counter will be set to 0, and the data will be saved in the register.? CPU will ignore the writing operations that write the different values. Q：Every bit at locations $30~$36 should be double written. Does it equal to the two consecutive bit operations? A: Yes.

Operation Voltage

Q: How many selections are offered for LVR? A: Two LVR selections: One reset is that system will generate LVR if the operation voltage is lower than 4V; the other reset is system will generate LVR if the operation voltage is lower than 2.5V.

Operation Speed

Q: What's the frequency of system clock in SPMC65 family MCU? How long does each instruction execute? A: In SPMC65 family MCU, the max. frequency of the external crystal oscillator is 16M Hz, and the system clock frequency will be acquired by dividing the input oscillator frequency by two, namely, the max. frequency of the system clock is 8M Hz. On average2-4 cycles an instruction has, so the average execution time for an instruction is 0.25~0.5us.

General IO

Q: How about the driving capability of I /O port in SPMC65 family MCU? A: The I/O port in SPMC65 family MCU has 4mA current driving capability, and 10mA current sinking capability. Some types of device even have up to 20mA current sinking capability. Q: What does slew rate function of I/O port mean in SPMC65 family MCU? A: If slew rate function on PB[7:6] needed to be enable, programming SLOWE bit in P_IO_Opt ($35.0) to "1" will enforce the output high to low transition time to 250ns ± 20% (determined by Fsys). This function is designed for long-distance communication between MCUs, which can prevent from EMI effectively. It is just like connect a capacitor in parallel to the communication pad. Q: How to set I/O port as pull-up/pull-down input in SPMC65x MCU? A: When an I/O port is in input state, on-chip MOS transistor circuit serves as a 100KΩ weak pull-up/pull-down resistor. But generally speaking, the additional external pull-up/pull-down resistor is needed to ensure the EMC capability of the system. For an input I/O port, it is the built in MOS transistor to make the port input with 100 pull up or pull down. Q: How do A / D analog voltage input signal, timer output signal and the data signals of SPI / UART / IIC realize the communication with peripheral devices? A: They realize the communication through multiplex I/O port. Detailed multiplex pin is defined as follows: Pin Special Function Pin Special Function PA7 ADC Analog Voltage Input PC3 SPI Data Output PA6 ADC Analog Voltage Input PC2 SPI Data Input PA5 ADC Analog Voltage Input PC1 SPI Clock Output / Clock Input PA4 ADC Analog Voltage Input PC0 SPI Chip Select PA3 ADC Analog Voltage Input PD7 Timer 5 Compare Output / PWM Output PA2 ADC Analog Voltage Input PD6 Timer 4 Compare Output / PWM Output PA1 ADC Analog Voltage Input PD5 External Interrupt 5 Input / Timer 5 Capture Input / Timer 5 External Event Input PA0 ADC Analog Voltage Input PD4 External Interrupt 4 Input / Timer 4 Capture Input / Timer 4 External Event Input PB7 ADC Analog Voltage Input or A/D External Reference Voltage Input PD3 Timer 2 Compare Output / PWM Output PB6 Buzzer Output PD2 Timer 3 Compare Output / PWM Output PB5 External Interrupt 1 Input / Timer 3 Capture Input / Timer 3 External Event Input PD1 External Interrupt 3 Input PB4 External Interrupt 0 Input / Timer 2 Capture Input / Timer 2 External Event Input PD0 External Interrupt 2 Input PB3 Timer 1 Compare Output / PWM Output PE7 PB2 Timer 0 Compare Output / PWM Output PE6 D/A Output PB1 Timer 1 Capture Input / Timer 1 External Event Input PE5 Comparator 1 Input PB0 Timer 0 Capture Input / Timer 0 External Event Input PE4 Comparator 1 Reference Input PC7 IIC Data Line PE3 Comparator 0 Input PC6 IIC Clock Line PE2 Comparator 0 Reference Input PC5 UART Receiving Signal PE1   PC4 UART Transmitting Signal PE0   Q: Does the state of I/O need to be initialized before its special function is enabled? A: some of ports need to be initialized before its special function is enabled. For example, the related I/O port should be set as input before the external interrupt input is enabled; similar to the capture input ports, serial communication interface ports. While part of ports don"t need to be initialized before their special functions are enabled, such as ADC input, DAC output, voltage comparator function, Buzzer output, PWM output and compare output. Q: How to deal with the I/O pin that is not used? A: On the hardware, to connect it to GND through a10K or greater resistor; on the software, to set it as output low voltage. Q: Does an I/O port need any external protection device if carrying telecommunication through it? A: The input function of SPMC65 family MCU is enabled by the Schmidt Trigger, therefore, the port boasts strong anti-jamming ability. However, in order to prevent interference from powerful interference source such as static electricity, it's better to make I/O in series with a resistor. Q: How to set I/O state to get the minimum power consumption in power saving modes? A: In order to save power, part of peripherals (ADC module, watchdog) that will not be used temporarily should be disabled before entering the STOP mode. First, set the port to be input and make sure there is no current flow in the port and peripheral circuit. As input, the port impedance is taken to be extremely high for the external circuit. As a result, current will not be generated. The normal input voltage should be VSS or VDD, otherwise, tiny current may be generated (1mA @ 2V.). Therefore, considering the existence of IO port and peripheral circuit, if the port is unfit for input, it can be set to be output. Peripheral circuit determines the output level to be high or low. For instance, if the pin is connected with a pull-up resistor, it can be configured to output high level ; if pull-down, it can be set to output low level. The following figure is to show the schematic diagram for IO ports when they"re used neither as input nor as output:

AD, DA Q: What's the internal reference voltage of ADC on SPMC65 family MCU? And how about the external voltage reference value? A: The ADC on the SPMC65 family MCU can select the top reference voltage, VDD; it can also select the external reference voltage value ranging in 2.0~VDD. Q: What's the top frequency of A / D conversion on SPMC65 family MCU? A: 100KHz. Q: What's the highest output current of DAC? A: 3.3mA. Q: What's the conversion frequency of DAC? A: A 10-bit DAC is built in SPMC65 family MCU, and, it takes 80us to run a conversion.

CCP (Capture, Compare, PWM) Q：In CCP mode, part of registers is mapped to the same address as that of the Count and Preload in the Timer mode. Is there anything to notice when they are read in the 16-bit mode? A: When reading in the 16-bit mode, they also follow the sequence that first reading low byte and then reading the high one. Q: Does any Timer with capture is able to capture a 16-bit cycle? A: Only Timer 5 can be set to capture the 16-bit cycle. Q: What is the hold function in the capture? A: Capture module provides user with function of holding input signal. User can assign the capture data hold selection bit in P_CAP_Ctrl to be 1 for holding captured data (width / cycle) till it is read out. Q: How to update the duty ratio register and cycle register in PWM mode? A: In 8/12/16-bit PWM mode, every Timer has corresponding cycle register and duty ratio register with following operations. 1. In 8-bit PWM mode, data should be written first into P_TMRx_PWMDuty, and then P_TMRx_PWMPeriod.(x=0,2,4) 2. In 12-bit PWM mode, when updating cycle, data should be written first into P_TMRx_DutyPeriod, and then P_TMRx_PWMPeriod; when updating duty ratio, data should be written first into P_TMRx_DutyPeriod, and then P_TMRx_PWMDuty.(x=1,3) In 16-bit PWM mode, when updating cycle, data should be written first into P_TMR5_DutyPeriodHi, and then P_TMR5_PWMPeriodLo; when updating duty ratio, data should be written first into P_TMR5_DutyPeriodHi, and then P_TMR5_PWMDutyLo.

Timer Q: What's the relationship between Watchdog Reset and Watchdog Timer? Do they perform the same function? A: The Watchdog Timer acts as counter and will trigger a watchdog interrupt when the timer overflows. Once watchdog interrupt are persisted for 8 times without clearing watchdog counter, CPU will reset automatically. This reset signal will be the time base of WDT uses the internal watchdog RC oscillator circuit and typical frequency is 25kHz. Q: Who provide the clock source for the Timer from on SPMC65 family MCU? Is it the system clock? A: There are 8 selections to get the counting frequencies for Timer, where 7 clock frequencies can be obtained via dividing the system clock by 1~512, thus the frequency input range is very wide; another selection can be obtained by counting the external event, namely Timer can count external signals. Q: What is the Timer counting egde of clock, rising or falling? A: At rising edge. Q: When Timer is running in 8-bit P mode, does higher 8-bit of a register operate? A: No. Q: If two Timers work at a time, will a collision happen? A: No. Q: How to load the 16-bit Timer value on SPMC65 family MCU? Will error take place? A:In SPMC65X family, if a chip equips with 8-bit CPU and data bus width is 8-bit, the user can’t access 16-bit data simultaneously. In order to overcome this limitation in 16-bit timer/counter mode, the Timer x MSB（x = 0~5）data registers are designed with extra read/write buffer, which is shown below. User must read the LSB Byte first and then the MSB byte that is buffered automatically. This buffered value remains unchanged until the 16-bit read sequence is completed. Moreover, user must write the MSB byte first that will be buffered automatically and then the LSB byte. This buffered value remains unchanged until the 16-bit write sequence is completed and the buffered MSB byte will download into Timer x with LSB byte simultaneously. Q: When using Timer, if an interrupt is disabled, will the interrupt flag be set 1? A: Yes, no matter enabling or disabling the interrupt, the flag will be set 1 if the timer overflows. The difference between interrupt enable and disable is whether the interrupt is responded and the interrupt service routine is entered. Time Base Q: What does time base mean? A: Time base can be considered as a simple Timer that only a few fixed frequencies can be selected. Interrupt Q: How many triggering modes does external interrupt have? A: External interrupt can be set to be level-triggered and edge-triggered. The edge-triggered can be at rising edge or falling edge; the level-triggered can be at high level or low level. However, trigger method of NMI interrupt can only be selected from the falling edge or rising edge. Q: What's the difference between NMI and IRQ? A: The main differences are as follows: NMI has higher PRI than IRQ, and no matter how the interrupt flag(I) indicates in the state register (P), CPU will receive NMI without exception; however, CPU will not receive IRQ unless the corresponding flag in the state register is cleared. NMI can only be set as edge-triggered; however, IRQ can be set as both edge-triggered and level-triggered. Only one interrupt can be set as NMI at a time; however, two or more interrupts can be set as IRQ-level simultaneously. Clock Q: How many clock source for SPMC65 family MCU? A: The PMC65 family MCU supports 3 clock resources: Crystal / Ceramic Resonator, RC oscillator, and external clock input. Different clock input can be selected via setting P_MO($7FE0). Note: If Crystal / Ceramic Resonator or external clock input are selected as the clock input source, the clock frequency will be divided by 2 to be the system clock frequency (FSYS) for the CPU. Therefore, if we wan to get 8M Hz system clock, Crystal / Ceramic Resonator or external clock must be set to16M Hz. Q: What are the machine cycle and the instruction cycle on SPMC65 family MCU? A: Oscillator clock frequency (FOSC) and system clock frequency (FSYS) are different here. FOSC means input crystal frequency or external clock frequency. It is up to 16M Hz. Half of FOSC is FSYS, the working frequency of CPU and peripheral devices. The machine cycle is 1/FSYS for current micro-controller, i.e., the cycle of the CPU clock and that of system clock are 1/FSYS. Here, a CPU clock cycle is regarded as a cycle unit. If the cycle of an instruction is 3, it means that the current instruction running needs 3 CPU clock cycles, (i.e., FSYS clock cycle). Q: What should be taken more notice when Crystal Resonator is selected as the system clock source? A: The resonator can be crystal one or ceramic one. Normally connect two 20pf ceramic capacitors to help oscillator start. The clock circuit is essential to the system stability. Therefore, as for the system which has low immunity to external interference or high demand for the stability, pay more attention to the PCB layout. The clock input line should be as short as possible, hence, the clock circuit can be close to IC; besides, the ground lines of the clock circuit should avoid the interference from other circuits. Q: Why does SPMC65 family MCU select RC Oscillator as system clock source? A: The RC circuit features simple structure and low cost. When using the RC Oscillator, SPMC65 family MCU can output oscillation signal in XO pin, which is synchronous and has the same oscillation frequency as that of the system. However the disadvantage is that the clock frequency generated by RC oscillation generates is not so precise so that it's not suitable for the system with a high degree of timer accuracy. Q: What is the clock source of Timer on SPMC65 family MCU? Is it the system clock? A: There are 8 selections to get the counting frequencies for Timer, where 7 clock frequencies are obtained via dividing the system clock by 1~512, thus the frequency input range is very wide; another clock source is counting by the external clock input, namely Timer can count external event. Communication Q: How many types of serial communication interface module does SPMC65 family MCU offer? A: SPMC65 family MCU offers three types serial communication interface modules. SPI ( Serial Peripheral Interface) Standard full-duplex UART ( Universal Asynchronous Receiver / Transmitter) IIC (Inter-Integrated Circuit) bus Q: How to clear the SPIIF, UARTIF and IICIF? A: User can read the interrupt flags of SPI, UART, IIC from the interrupt flag register P_INT_Ctrl2; but user can not directly write data to the register for changing their status. The interrupt flags are cleared by the related control registers. The SPIIF can be cleared by writing bit 7 of P_SPI_Status by 1; The IICIF can be cleared by writing bit 4 of P_IIC_Status by 1; To clear UARTIF, the UARTIF will be automatically cleared when reading data from P_UART_Data; and TXIF will be automatically cleared when writing data into P_UART_Data. UART interrupt flag is determined by both interrupt receiving flag RXIF and interrupt transmission flag TXIF. After clearing RXIF or TXIF, UARTIF will be automatically cleared (ensure that both RXIF and TXIF are set to be 0) Q: In SPI communication, when the clock frequency of SPI is 1M Hz and the sampling clock frequency is set to be 2M Hz, why do communication errors always happen? A: The purpose of sampling clock is to prevent received data from glitch noise, but lower sampling clock would affect the speed of communication. Sampling clock frequency > = 4×SPI clock frequency is recommended. When the SPI clock frequency is 1M Hz, the sampling clock frequency >= 4×1M Hz = 4M Hz, namely the sampling clock frequency must be higher than 4 M Hz to ensure the slave device can receive the right data. Here the sampling clock should be set as 4M Hz. Q: What does BUFFULL bit mean in SPI communication? A: In SPI communication, if a full data, i.e., one byte data is received, the received buffer is overwritten by it, here the BUFFULL bit will be set 1. Q: How the SPMC65 family MCU implement the full-duplex communication through only one Data Register P_UART_Data? A: On SPMC65 family MCU the data registers used for UART communication include data receiving buffer and data transmission buffer, while both of them are called P_UART_DATA. Reset Mode Q: What's the voltage value of LVR on SPMC65 family MCU? A: When the power supply voltage value is lower than the desired value for more than 1024 system clock cycles, the chip will be reset. SPMC65 MCU offers 4V and 2.5V reset voltages. Q: What's the corresponding reset time for each reset mode on SPMC65 MCU? A: No delay is needed after IAR and WDR. In POR mode, when the voltage is raised to 1.45V, the system will wait for 40ms for power supply stabilization and another 40ms for system clock stabilization and then 1024 system clock cycles the reset will be finished. LVR reset will occur when the power is lower than the certain level and if the power remained low for 1024 cycles of system clock. And it will be extended with additional 1024 cycles of system clock before the normal running. External reset will generate if the voltage of external reset pin is lower than 0.3xVDD and it remains low for more than 200ns. If the recharging voltage becomes acceptable, it remains a 40 ms for system clock stabilization and then additional 1024 cycles of system clock before the normal running. Q: Will "External Reset" reset all the content in user RAM location? A: No, External Reset belongs to system reset (including CPU reset). The hardware control register will be initialized. The data in user RAM location will not be changed unless the voltage falls to certain value that can"t hold the data in user RAM location. Q: How long does it take from Power-on Reset to Analog-to-Digital Converter (ADC) is ready for running? And how long does it take from that quitting from the STOP mode and entering the normal mode to that ADC is ready for running? A: After Power-On Reset, the ADC setup time is equal to that for settling the top reference voltage, which depends on the capacitance connected in VREF pin. The greater the capacitance is, the lower the noise of VREF and ADC conversion result is. If the capacitance is 4.7uF, the settle time is probably 2ms; if there is no by-pass capacitor (not recommendable), the time for settlement is probably 10us. Note: Before AD conversion, tracking time should be 1.5us, which determines the switching speed of ADC multiplexer switch (MUX). After MCU quits from STOP mode and enters the normal operation mode, period from ADC becoming settled to starting conversion is equal to that in Power-On Reset. Q: What influence will each reset make upon the register and RAM? A: In terms of result reset can be classified into system reset and CPU reset. System reset will reset all of the system including CPU (IO, Timer, A/D, D/A, and different controllers); however, CPU reset will reset CPU only, namely PC pointer will point to the initialization address again; the program runs from the beginning and the SP is also reset to point to the highest address. Here, IAR and WDR just affect the PC pointer and SP, while POR, RESET and LVR can reset CPU and initialize hardware control registers. Q: In the STOP mode, when CPU woken by external reset, will the register, RAM and hardware modules be affected as usual (namely not in the STOP mode)? A: Yes. In fact, it's an abnormal case to make SPMC65 MCU enter normal operating mode via external reset in the STOP mode or HALT mode. It is equal to the external reset. Q: In STOP and HALT modes, does Watchdog Timer (WDT) run? A: The clock source of SPMC65 MCU WDT is gotten from the on-chip RC oscillation circuit. In the HALT mode, all the peripherals keep the original running state and run normally, except that only CPU stops for power saving; at this time WDT runs normally; in the STOP mode, on-chip RC oscillator stops working, CPU and all peripherals also stop. At this time whether WDT runs normally lies on the watchdog setting before entering STOP mode, if the watchdog is set to be enabled in the STOP mode, it will run normally and wake up CPU from the STOP mode with watchdog interrupt; if the watchdog is set to be disabled in the STOP mode, it will stop running. Q: What's the relationship between Watchdog Reset and Watchdog Timer? Do they perform the same function? A: The Watchdog Timer is used to generate time signal. Counter Overflow in Watchdog Timer will generate a watchdog interrupt. Watchdog Reset signal will generate if 8 continuous interrupts are generated. The clock source is from the RC oscillation circuit, and the oscillation frequency is 25K Hz. Q: When does an IAR occur? A: When an instruction is fetching from an address out of the working area, and the stack is overflowed, IAR generates. Q: What are functions of SEI and CLI? A: Running SEI can set the interrupt disable flag (I flag) of the state register P to "1". Now, CPU will ignore every interrupt request except for NMI. But, CLI can clear I flag and CPU will be enabled to receive all the interrupt sources. Q: Is instruction cycle added by 1 for cross bank addressing? A: Yes. The memory size is 256-Byte for one page. Q: Which instruction will be affected by the decimal mode? A: The decimal mode has a hold on ADC and SBC. By decimal mode, they all run the decimal arithmetic operations. SED　　　　　　　　　; Set D flag to 1 to enter the decimal mode LDA　　　#$25　　　　; A<-$25 SEC　　　　　　　　　; Set carry flag C to 1 ADC　　　#$18　　　　; Decimal arithmetic operation, A ? (BCD)A + (BCD)$18 + C, 　　　　　　　　　　 ;the A accumulator is set to $44, C=0, N=0, Z=0, V=0 Q: What is function of the BIT instruction? What is difference between the BIT and TST? A: BIT can test bit in memory with accumulator A by doing AND operation on every bit. The AND result is not saved, i.e., it doesn"t change the accumulator value and the memory value. It can change the flag value of N, V, Z of state register. TST is a bit operation instruction for judging a certain bit; it changes the Z flag only. Q: Is the bit operation instructions only enabled in page 0? A: Yes. It can only operate the registers and memory unit of page 0. Stack Q: What is SPMC65 stack mapping? A: The SPMC65 stack contains 32-byte. At least 3-byte is needed for one interrupt context saving: 2 bytes for return address and 1 byte for the status register. Before entering an interrupt, A, X, Y are often pushed into stack, too. Therefore, 6 bytes of memory are often required and at most 5 layer interrupts are embedded. 2 bytes are occupied for a subroutine, therefore, 16 layers at most are embedded. If the stack is out of default memory, illegal address interrupt will occur. Instruction Q: How to use the C, D, V flags? Carry flag: This bit is set to 1 if the result of the addition operation generates a carry, or if the result of subtraction doesn"t generate a borrowing. In addition, the Shift Instructions and Rotate Instructions also change this bit. Decimal mode flag: This flag indicates what arithmetic operation mode is operated. The current family has two operation modes which are binary mode and decimal mode for the arithmetic operation. User can run the instruction to alternate between them. Overflow flag: This flag indicates whether the overflow has occurred in the arithmetic operation. When the result of an addition or subtraction is over +127 or less -128, this overflow bit is set to "1". Q: What is difference between the machine cycle and the instruction cycle? A: Oscillator clock frequency (FOSC) and system clock frequency (FSYS) are different here. FOSC means input crystal frequency or external clock frequency. It is up to 16M Hz. Half of FOSC is FSYS, the working frequency of CPU and peripheral devices. The machine cycle is 1/FSYS for current micro-controller, i.e., the cycle of the CPU clock and that of system clock are 1/FSYS. Here, a CPU clock cycle is regarded as a cycle unit. If the cycle of an instruction is 3, it means that the current instruction running needs 3 CPU clock cycles, i.e., FSYS clock cycle. Q: Why two or more NOP instructions should follow the instructions that for entering HALT or STOP modes? Without these NOP instructions, will the system execute the instructions following the instructions that for entering the HALT or STOP modes? A: Normally, after being waken up from the power saving mode, no user program is run rightly to prevent it from error running resulted by the unstable system clock. Therefore, two or more NOP instructions, that do no operation, should follow the instructions that for entering HALT or STOP modes. In this way, even though NOP is executed before the system clock becomes settlement, the system will not be influenced. It provides more reliability for the system operation. Q: What's the difference between .PAGE0 and .DATA when defining variable in data memory? A: .PAGE0 is used to define a variable in page0; and .DATA for the non page0 ones. In SPMC65x devices, PAGE0 ranges $0000~$00FF which includes hardware control registers memory and part of user-defined RAM. Other RAM space is provided for DATA segment. The access to page0 is faster than to DATA segment; bit operation instruction can only read and write data in page0. Q: What is the error of the variable definition? A: Variable name should be placed at the first position of the line or follow a colon if in other position. For example: Q: Which bit operation instructions are supported here? A: SET----- Set Set BITn of specified address as "1" ? CLR----- Clear BITn of specified address as "0". ? INV----- Toggle BITn of specified address. ? TST----- Read and judge BITn is zero of specified address Q: How to create a data table in program memory? A: It is similar to define a data table in RAM segment. Be sure ".CODE" is placed before the data table definition in the program. For example: .CODE　　　　　　　　　　　　　　　　　　　　　　;Code Section T_DataTable:　　　　　　　　　　　　　　　　　　　;The com table of led 　　 DB　　　　　　　　%00001110　　　　　; Data "1" 　　 DB　　　　　　　　%00001101　　　　　; Data "2"　　　 　　 DB　　　　　　　　%00001011　　　　　; Data "3" 　　 DB　　　　　　　　%00000111　　　　　; Data "4" Q: When does an IAR operation occur? A: When an instruction is fetching from an address out of the working area, and the stack is overflowed, IAR generates. Q: Is there any other requirements for doing double write operations to every bit at locations $30~$36? A: For every double write register, double clearing counter is enabled. After the first write operation, it generates an internal tag; if the register is written with an equal data again, the counter will be set to 0, and the data will be saved in the register.? CPU will ignore the writing operations that write the different value. Q: Every bit at locations $30~$36 should be double written. Does it equal to the two consecutive bit operations? A: Yes. Q: How many cycles does an instruction need generally? A: The instruction cycle varies from 2~4 or 5, 6 CPU clock cycles. Q: What are the features of the Sunplus SPMC65 MCU instruction set? A: It features the CICS for flexible application and high running performance. Q: Which program directive is used to define a constant, and, which to a variable? A: Constant definition: .DB, .DW, .DD, .DOUBLE which can coordinate with .EQU Variable definition: .DS Constant definition directive is able to define a variable. But the definition is not recommended. Q: How many bytes does the .DD directive "ef" occupy? A: Every constant that is defined from .DD occupies four-byte. Therefore, the string "ef" occupies eight-byte of memory. Q: What is the difference between .VAR and .EQU? A: .VAR and .EQU are both used to assign value for label. .VAR can reassign different value to the label that had assigned by it, and the label is declared to be a private one. .While EQU doesn"t reassign. A label, being assigned by .EQU, can be declared as public label for being cited by another file. Q: What is the difference between .VAR, .EQU and .DB, .DW? A: .VAR and .EQU are both used to assign value for a label; they do not occupy any memory space, and can be posited to any place of the program. .DB and .DW are to define a constant; they occupy memory for storing constant. Constant definition directive is posited below the .CODE segment and the user-defined .ROM segment. Q: Can user define the start address of .CODE segment? How to define? A: Changing start address of a segment from prog.lik is not recommended. User can change it by modifying the xxxxh of "locate: CODE at xxxxh" in the prog.lik from the current project folder. Q: When compiling the following program, why an error as shown below occurred? A: A space character is needed between "comment" and "@".