•  SPMC65 CPU
　 - 182 instructions
　 - 11 addressing modes
　 - Up to 8M Hz system clock frequence
　 - Bit operation instructions (Set, Clear, Inverse, and Test)
•  Memory Size
　 - 2K bytes OTP ROM with configurable secrecy function
　 - 192 bytes of RAM
•  I/O Port
　 - 15/11 multifunctional bidirectional I/O ports
　 - All I/O ports are Schmidt trigger input
　 - Programmable input ports with pull-high/low resistor or floating
　 - All I/O ports with the led driving ability
　 - 2 I/O ports with 20mA sink current
•  Interrupt Management
　 - External interrupts, NMI and IRQ
　 - Two external interrupts, thereinto, one can be set to NMI
　 - Seven internal interrupt
•  Reset Management
　 - Power On Reset (POR)
　 - Low Voltage Reset (LVR)
　 - Watchdog Timer Reset(WDR)
　 - External Reset(ERST)
　 - Illegal Address Reset (IAR)
•  Clock Management
　 - Clock selection: Crystal resonator, RC oscillator, external clock input
　 - Under RC mode, the clock signal is output
•  Power Management
　 - Two power saving modes: STOP and HALT

•  Two peripheral analog circuit
　 - Nine 10-bit ADC(100k Hz)
　 - Low voltage reset(2.5V/4V)
•  One 8-bit Timer/Counter(Timer0)
　 - Timing/counting function
　 - 8-bit capture function
•  One 16-bit Timer/Counter(Timer1)
　 - Timing/counting function
　 - 8-bit/16-bit capture function
　 - 16-bit compare output
　 - 12-bit PWM output
•  Time base
　 - Frequence: 1Hz ~ 62.5kHz @8MHz(system clock)
　 - 15-stage frequence division
•  Buffer Output
　 - Frequence: 1kHz ~ 2MHz @8MHz(system clock)
　 - 12-stage frequence division
•  Programmable watchdog timer
　 - Interrupt frequence: 1.5Hz ~ 195Hz