•  SPMC65 CPU
　 - 182 instructions
　 - 11 addressing modes
　 - Up to 8MHz clock operation
　 - Supports bit operation instruction (Set, Clear, Inverse, Test)
•  Memories
　 - 2K bytes program memory (OTP) with security protection
　 -128 bytes RAM including stack area
•  I/O Port
　 - 19/13 multifunction bi-directional I/Os
　 - All I/Os are Schmitt Trigger inputs
　 - Each incorporate with pull-up resistor, pull-down resistor or floating input, depending
　 - on programmer's settings on the corresponding registers
　 - I/O ports with LED driving capability
2 I/O ports with 20mA current sink
•  Interrupt Management
　 - Interrupt option: NMI or IRQ for external interrupts.
　 -1 external interrupts (able be programmed as NMI).
　 -4 Internal interrupts.
•  Reset Management
　 - Power On Reset (POR)
　 - Low Voltage Reset (LVR)
　 - Watchdog Reset (WDR)
　 - External Reset (ERST)
　 - Illegal Address Reset (IAR)

•  Clock Management
　 - Three clock sources: RC-oscillation, crystal input and external clock input
　 - Clock output capability for RC-oscillation
•  Power Management
　 - 2 power saving modes: STOP, HALT mode
•  Analog Peripheral
　 - LVR: Low Voltage Reset (2.5V/4V)
•  One channels of 16-bit Timers (Timer0)
　 - Timers, Event counter mode
　 - Capture (8-bit with width/cycle measurement or 16-bit with width measurement)
　 - 16-bit and 8-bit compare output
　 - 8-bit PWM output
•  Time Base Interval Timer
　 - Frequency: 1Hz to 62.5kHz @Fsys=8MHz
　 - 15 stages pre-scale option

•  Buzzer Output
　 - Frequency: 1kHz to 2MHz @Fsys=8MHz
　 - 12 stages pre-scale option

•  Configurable Watchdog Timer
　 - Frequency: 1.5Hz to 195Hz @Fsys=8MHz